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PI90LVB16
Features
Master/Slave clock selection in a backplane application 160 MHz operation (typical) 100ps duty cycle distortion (typical) 50ps channel to channel skew (typical) 3.3V power supply design Glitch-free power on at CLKI/O pins Low Power design (16mA @ 3.3V static) Accepts small swing (300mV typical) differential signal levels Industrial temperature operating range (40C to +85C) Available in 24-pin TSSOP Packaging (L)
General Description
3V Bus LVDS 1-to-6 Clock Buffer/Bus Transceiver
PI90LVB16 is a six-channel LVTTL clock distribution driver with 50 picosecond channel-to-channel skew. It translates one BLVDS (Bus Low-Voltage Differential Signaling) input signal into six LVTTLcompatible output signals for distribution to adjacent chips on the same board. The PI90LVB16 accepts BLVDS (300mV typical) differential input levels, and translates them to 3V CMOS output levels. The 160MHz PI90LVB16 can be the master clock, driving inputs of other clock I/O pins in a multipoint environment. It can also drive the BLVDS backplane with a separate channel acting as a return/ source LVTTL clock source. The master/slave clock selection of the driving source is controlled by the CrdCLKIN and the DE pins. An output enable pin OE, when high, forces all CLKOUT pins high. A backplane clock distribution network must be able to drive many transmission line stubs. The Bus LVDS feature of the PI90LVB16 is ideal for driving data transfers in large, high-performance backplane system applications. The device can be used as a source synchronous driver to distribute clock signals within data and telecommunications systems.
Driver Mode Truth Table
Input OE L L H H H DE L L L L H CrdCLKIN CLKI/O+ L H L H X L H L H Z Output CLKI/O H L H L Z CLKOUT L H H H H
Receive Mode Truth Table
Input OE DE H L L H H H CrdCLKIN X X X (CLKI/O+)(CLKI/O) X VID 0.07V VID 0.07V Output CLKOUT H H L
L = Low Logic State; H = High Logic State; X = Irrelevant Z = High Impedance
Function Diagram
CLKOUT0 CLKOUT1 OE CLKI/0+ R CLKI/0- Delay CLKOUT5 MUX
D
DE CrdCLKIN
1
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PI90LVB16 3V Bus LVDS 1-to-6 Clock Buffer/Bus Transceiver
Connection Diagram
GND OE NC VCCA GNDA CLKI/0+ CLKI/0- GNDA CrdCLKIN NC DE GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 VCC CLKOUT0 GND CLKOUT1 VCC CLKOUT2 GND CLKOUT3 VCC CLKOUT4 GND CLKOUT5
24-Pin L
20 19 18 17 16 15 14 13
TSSOP Package Pin Description
Pin Name CLKI/O+ CLKI/O OE Pin # 6 7 2 Type I/O I/O I De s cription True (Positive) side of the differential clock input. Complementary (Negative) side of the differential clock input. OE; this pin is active Low. When High, this pin forces all CLKOUT pin High. When Low, CLK OUT pins logic state is determined by either the CrdCLKIN or VID at the CLKI/O pins with respect to the logic level at the DE pin. This pin has a weak pullup device to VCC. If OE is floating, then all CLK OUT pins will be High. DE; this pin is active Low. When Low, this pin enables the CardCLKIN signal to the CLKI/O pins and CLK OUT. When High the Driver is 3- State, the CLKI/O pins are inputs and determine the state of the CLK OUT pins. This pin has a weak pullup device to VCC. If DE is floating, then all CLKI/O pins are 3- State. Six Buffered clock (CMOS) outputs. Input clock from Card (CMOS level or TTL level). VCC; Analog VCCA (Internally separate from VCC, connect externally or use separate power supplies). No special power sequencing required. Either VCCA or VCC can be applied first, or simultaneously apply both power supplies.
DE
11
I
CLK OUT CrdCLK IN VCC
13,15,17,19,21,23 9 16,20,24
O I Power
GND VCCA
1,12,14,18,22 4
Ground GND Power Analog VCCA (Internally separate from VCC, connect externally or use separate power supplies). No special power sequencing required. Either VCCA or VCC can be applied first, or simultaneously apply both power supplies.
GNDA NC
5,8 3,10
Ground Analog Ground (Internally separate from Ground must be connected externally. No Connects.
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PI90LVB16 3V Bus LVDS 1-to-6 Clock Buffer/Bus Transceiver
Absolute Maximum Ratings(1)
Supply Voltage Range, VCC ..................................................................................... 0.3V to +4V Enable Input Voltage (DE, OE, CrdCLKIN) .............................................. 0.3V to +4V Voltage (CLKOUT) ............................................................... 0.3V to (VCC + 0.3V) Voltage (CLKI/O) ............................................................... 0.3V to (VCC + 0.3V) Driver Short Circuit Current ....................................................................... momentary Receiver Short Circuit Current .................................................................. momentary Maximum Package Power Dissipation at +25C TSSOP Package ................................................................................... 1500mW Derate TSSOP Package ..................................................... 8.2mW/C above +25C JA ........................................................................................................................................... 95C/W JC ........................................................................................................................................... 30C/W Storage Temperature Range ............................................................. 65C to +150C Lead Temperature Range (Soldering, 4s) ........................................................... 260C ESD Ratings: HBM(2) .................................................................................................................. 9kV CLKOUT(05) .......................................................................................................................... 2kV CDM(2) .................................................................................................................................. >1000V Machine Model(2) ............................................................................................................... >200V
Recommended Operating Conditions
Min. Supply Voltage (VCC) +3.0 CrdCLKIN, DE, OE Input Voltage 0 Operating Free Air Temperature (TA) 40 Typ. +3.3 24 Max +3.6 VCC +85 Units V V C
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PI90LVB16 3V Bus LVDS 1-to-6 Clock Buffer/Bus Transceiver
DC Electrical Characteristics
Symbol VTH VTL VCMR IIN VOH1R VOH2R VOL1R VOL2R IODHR IODLR VIH VIL IIH IIL IINCRD VCL Parame te r Input Threshold High Input Threshold Low
Over Supply Voltage and Operating Temperature ranges, unless otherwise specificed(3,4)
Conditions Pin M in. Typ. 25 70 CLKI/O+, CLKI/O VID/2 10 VCC 0.2 VCC 0.6 CLKOUT 5 2.9 2.5 0.04 0 16 14 DE, OE, CrdCLKIN VIN = VCC or 2.4V VIN = GND or 0.4V VIN = 0V to VCC, OE = VCC IOUT = 1.5mA OE = DE = 0V, CrdCLKIN = VCC or GND, CLKI/O() = Open CLK OUT (0:5) = Open Circuit OE = GND, DE = VCC, CrdCLK IN = VCC or GND, VID = 250mV (0.125V VCM 2.275V) CLK OUT(0:5) = Open Circuit DE = OE = 0V, CrdCLK IN = VCC or GND, RL = 37.5 between CLKI/O+ and CLKI/O, CLKOUT (0:5) = Open Circuit 2.0 GND 6 20 5 0.8 4 11 0.22 24 25 0.1 0.4 34 37.5 VCC 0.8 6 +20 5 V A mA V 35 2.8 VID/2 +10 M ax. 75 Units mV
Common Mode Voltage VID = 250mV peak- to- peak Range(5) Input Current Output High Voltage Output High Voltage Output Low Voltage Output Low Voltage CLKOUT Dynamic Output Current(6) Input High Voltage Input Low Voltage Input High Current Input Low Current Input Current Input Voltage Clamp No Load Supply Current Outputs Enabled, No VID Applied No Load Supply Current Outputs Enabled, VID over Common Voltage Range Driver Loaded Supply Current VIN = OV to VCC, DE = VCC, OE = VCC, Other Input = 1.2V 50mV VID =250mV, IOH = 1.0mA VID =250mV, IOH = 6mA IOL =1.0mA, VID = 250mV IOL =6mA, VID = 250mV VID = +250mV, VOUT = VCC1V VID = 250mV, VOUT = 1V
V A
V
OE, DE CrdCLK IN OE, DE, CrdCLKIN
ICC
10
ICC1
VCC
6
mA
ICCD
16
21
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PI90LVB16 3V Bus LVDS 1-to-6 Clock Buffer/Bus Transceiver
DC Electrical Characteristics (continued)
Symbol VOD VOD VOS VOS VOHD VOLD IOS1D IOS2D IOS3D IOS4D IOS5D IOFF Parame te r Driver Output Differential Voltage Driver VOD Magnitude Change Driver Offset Voltage Driver Offset Voltage Multitude Change Driver Output High Driver Output Low Driver Differential Short Circuit Current(6) Driver Differential Short Circuit Current to VCC(6) Driver Differential Short Circuit Current to GND(6) Power Off Leakage Current
Over Supply Voltage and Operating Temperature ranges, unless otherwise specificed(3,4)
Conditions Pin M in. 250 Typ. 350 2 RL = 37.5, Figure 5 DE = 0V 1.1 1.25 1 1.4 CLKI/O+, CLKI/O 0.8 1.05 13 11 10 15 15 17 17 17 17 17 20 A M ax. 450 mV 20 1.5 20 1.8 V mV Units
V
CrdCLKIN = VCC or GND, VOD = 0V, (outputs shorted together), DE = 0V CrdCLKIN = GND, DE = 0V, CLKI/O+ = VCC CrdCLKIN = VCC, DE = 0V, CLKI/O = VCC CrdCLKIN = VCC, DE = 0V, CLKI/O+ = 0V CrdCLKIN = GND, DE = 0V, CLKI/O = 0V VCC = 0V or Open, VAPPLIED = 3.6V
mA
Switching Characteristics
Differential Receiver Characteristics
Symbol tPHLDR tPLHDR tSK1R tSK2R tSK3R tTLHR tTHLR tPLHOER tPHLOER fMAX
Over Supply Voltage and Operating Temperature ranges, unless otherwise specificed(7,8)
Parame te r Differential Propagation Delay High to Low. CLKI/O to CLKOUT Differential Propagation Delay Low to High. CLKI/O to CLKOUT Duty Cycle Distortion(10) pulse skew, tPLH tPHL Channel- to- Channel Skew; Same Part- to- Part Skew(12) Transition Time Low- to- High(9), (20% to 80%) Transition Time High- to- Low(9), (80% to 20%) Propagation Delay Low- to- High (O E to CLKOUT) Propagation Delay High- to- Low (O E to CLKOUT) Maximum O perating Frequency(15)
5
Conditions
M in. 1.3 1.3
Typ.(1) 2.6 2.6 5 5
M ax. 3.8 3.8 400 80 TBD 2.4 2.4 3.2 3.2
Units ns ps
Edge(11)
CL = 15pF VID = 250mV Figures 1 & 2 1.0 1.0 CL = 15pF Figures 3 & 4 1.0 1.0 100
1.4 1.3 2.1 2.1 160
ns
MHz
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PI90LVB16 3V Bus LVDS 1-to-6 Clock Buffer/Bus Transceiver
Switching Characteristics
Symbol tPHLDD tPLHDD tPHLCrd tPLHCrd tSK1D tSK2D tTLHD tTHLD tPHZD tPLZD tPZHD tPZLD fMAX
Notes:
Differential Driver Timing Requuirements
Parame te r
(Over supply voltage and operating temperature ranges, unless otherwise specificed(7,8)
Conditions CL = 15pF RL = 37.5 Figures 6 & 7 CL = 15pF Figures 8 & 9
M in. 1.0 1.0 2.0 2.0
Typ.(1) 1.5 1.3 2.8 2.8
M ax. Units 2.2 2.2 4.5 4.5 600 ps TBD ns
Differential Propagation Delay High to Low. CrdCLKIN to CLK I/O Differential Propagation Delay Low to High. CrdCLKIN to CLK I/O CrdCLKIN to CLKOUT Propagation Delay High to Low CrdCLKIN to CLKOUT Propagation Delay Low to High Differential Skew tPLH tPHL(13) Differential Part- to- Part Skew(14) Differential Transition Differential Transition Time(9), Time(9), (20% to 80%) (80% to 20%)
CL = 15pF Figures 6 & 7
0.2 0.2
0.35 0.35
0.65 0.65 2.6 2.6 4.3 3.6 ns
Transition Time Low to 3- State. DE to CLK I/O Transition Time Low to 3- State. DE to CLK I/O Transition Time 3- State- to- High. DE to CLK I/O Transition Time 3- State- to- Low. DE to CLK I/O Maximum O perating Frequency(15)
VIN = 0V to VCC CL = 15pF RL = 37.5 Figures 10 & 11 100 160
MHz
1. Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. These ratings are not meant to imply that the devices should be operated at these limits. The table of Electrical Characteristics specifies conditions of device operation. 2. ESD Rating: ESD qualification is performed per the following: HBM (1.5k, 100pF), Machine Model (250V, 0), IEC 1000-4-2. All VCC pins connected together, all ground pins connected together. 3. Current into device pins are defined as positive. Current out of device pins defined as negative. All voltages are referenced to ground except VID, VOD, VTH, and VTL 4. All typicals are given for: VCC = +3.3V and TA = +25C. 5. The VCMR range is reduced for larger VID. Example: If VID=400 mV, then VCMR is 02V to 2.2VAVID up to VCC-0V may be applied between the CLKI/O+ and CLKI/O inputs, with the Common Mode set to VCC/2. 6. Only one output should be momentarily shorted at a time. Do not exceed package power dissipation rating. 7. CL includes probe and fixture capacitance. 8. Generator waveform for all tests unless otherwise specified: f = 25 MHz, Zo = 50, tr = 1ns, tf = 1ns (10%90%). To ensure fastest propagation delay and minimum skew, clock input edge rates should not be slower than 1ns/V; control signals not slower than 3ns/V. In general, the faster the input edge rate, the better the AC performance, 9. All device output transition times are based on characterization measurements and are guaranteed by design. 10. tSKIR is the difference in receiver propagation delay tPLH-tPHL of one device, and is the duty cycle distortion of the output at any given temperature and VCC. The propagation delay specification is a device-to-device worst case over process, voltage and temperature. 11. tSK2R is the difference in receiver propagation delay between channels in the same device of any outputs switching in the same direction. This parameter is guaranteed by design and characterization. 12. tSK3R part-to-part skew, is the difference in receiver propagation delay between devices of any outputs switching in the same direction. This specification applies to devices over recommended operating temperature and voltage ranges, and across process distribution. tSK3R is defined as Max-Min differential propagation delay. This parameter is guaranteed by design and characterization. 13. tSK1D is the difference in driver propagation delay tPLH-tPHLand is the duty cycle distortion of the CLKI/O outputs. 14. tSK2D part-to-part skew, is the difference in driver propagation delay between devices of any outputs switching in the same direction. This specification applies to devices over recommended operating temperature and voltage ranges, and across process distribution. t SK2D is defined as Max-Min differential propagation delay. 15. Generator input conditions: trtf < 1ns, 50% duty cycle, differential (1.10V to 1.35V pk-pk). Output Criteria: 60%/40% duty cycle, VOL(max) 0.4V, VOH(min) 2.7V, Load - 7pF (stray plus probes). 6
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PI90LVB16 3V Bus LVDS 1-to-6 Clock Buffer/Bus Transceiver
Parameter Measurement Information
CLKI/0+ Generator CLKI/0- 509 D.U.T. CL CLKOUT
Figure 1. Receiver Propagation Delay and Transition Time Test Circuit
CLKI/0- VID = 250mV CLKI/0+ tPLHDR 80% VCC/2 CLKOUT 20% tTLHR tTHLR tPHLDR 80% VCC/2 20%
+1.35V +1.10V
VOH
VOL
Generator waveform for all test unless otherwise specificed: f = 25MHz, 50% Duty Cycle, Z0 = 509, tTHL = 1ns
Figure 2. Receiver Propagation Delay and Transition Time Waveforms
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Parameter Measurement Information
Test Point Generator 509 0.95V - 1.2V + 0.95V CL CLKOUT OE Test Point
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PI90LVB16 3V Bus LVDS 1-to-6 Clock Buffer/Bus Transceiver
Figure 3. Output Enable (OE) Test Circuit
OE
50% 50%
VCC
0V
tPHLOER tPLHOER
CLKOUT S1- = 0.95V S1+ = 1.2V
VOH
50% 50%
VOL
CLKOUT
S1- = 0.95V S1+ = 1.2V
VOH
Figure 4. Output Enable (OE) Delay Waveforms
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PI90LVB16 3V Bus LVDS 1-to-6 Clock Buffer/Bus Transceiver
Parameter Measurement Information
2V D 0.8V DE
RL/2 = 18.759
VOS VOD
RL/2 = 18.759
Figure 5. Differential Driver DC Test
CL CrdCLKIN
D
CL DE
RL
Figure 6. Driver Propagation Delay Test Circuit
VCC 50% CrdCLKIN tPLHCrd CLKI/0- 0 Differential CLKI/0+ tPHLDR 80% VDIFF= [CLKI/)+] - [CLKI/)-] 20% tTLHDD tTHLDD 0 Differential 20% 80% VOL tPHLCrd VOH 0V
Figure 7. Driver Propagation Delay and Transition Time Waveforms
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PS8536A
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PI90LVB16 3V Bus LVDS 1-to-6 Clock Buffer/Bus Transceiver
Parameter Measurement Information
Generator
CrdCLKIN
D.U.T. CL
CLKOUT
509
Figure 8. CrdCLKIN Propagation Delay Time Test Circuit
VCC CLKIN 0V
50% 50%
VOH CLKOUT
50% 50%
VOL
tPLHCrd tPHLCrd
Figure 9. CrdCLKIN Propagation Delay Time Waveforms
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PI90LVB16 3V Bus LVDS 1-to-6 Clock Buffer/Bus Transceiver
Parameter Measurement Information
VCC 0V
CL
CrdCLKIN
RL/2 1.2V
D
CL RL/2
Pulse Generator
DE 509
Figure 10. Driver 3-State Test Circuit
VCC DE 50% 0V tPLZD CLKI/O+ (CrdCLKIN - L) CLKI/O- (CrdCLKIN - H) tPZLD 1.2V 50% 50% VOL tPHZD CLKI/O+ (CrdCLKIN -H) CLKI/O- (CrdCLKIN - L) 50% tPZhD VOH 50% 1.2V
Figure 11. Driver 3-State Waveforms
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Ordering Information
Orde ring Code PI90LVB16L Package Name L24 Package Type 24- pin TSSO P Ope rating Range 40C to 85C
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PI90LVB16 3V Bus LVDS 1-to-6 Clock Buffer/Bus Transceiver
24-Pin TSSOP (L) Package
24
.169 .177
4.3 4.5 .004 .008 0.09 0.20
1
.303 .311 7.7 7.9
0.45 0.75 .047 1.20 Max
.018 .030
SEATING PLANE
.252 BSC 6.4
.0256 BSC 0.65
.007 .012 0.19 0.30
.002 .006
0.05 0.15
X.XX DENOTES CONTROLLING X.XX DIMENSIONS IN MILLIMETERS
Pericom Semiconductor Corporation 2380 Bering Drive * San Jose, CA 95131 * 1-800-435-2336 * Fax (408) 435-1100 * http://www.pericom.com
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